| 职位描述： |
Description:
Write, maintain and verify VHDL RTL code to meet functional specifications. Detailed knowledge of SONET (STS and VT processing) or SDH standards is preferred. Synthesis experience is required. Candidate should be well versed in efficient, high speed, synchronous design techniques. C and Perl programming skills desired. Experience with System C, PLI/FLI and QuickBench experience is also desired.
Essential Duties & Responsibilities:
§ Create/maintain VHDL RTL designs to meet functional specifications
§ Provide synthesis and physical design support
§ Write and execute a verification test plan
§ Create and automate test cases using C and Perl languages
§ Able to work in a team environment
§ Must have good English verbal and written skills
岗位要求：
按照设计规范编写，维护和验证 VHDL 代码，具有综合和静态时序分析的工作经验，精通高速同步电路的设计技巧，掌握 C 和 Perl 编程技巧者和有 SystemC, PLI/FLI 和 QuickBench 经验佳；具有 SONET(STS, VT processing)/SDH 专业知识者优先
岗位职责：
1. 按照设计规范实现和维护 VHDL 设计
2. 提供综合和物理设计支持
3. 编写和执行验证计划
4. 用 C 和 Perl 生成和自动测试 test cases
5. 良好团队协作能力
6. 必须具有良好的英语口语和书写能力 |